Federica Di Lauro

PhD student at Università di Milano Bicocca

I have developed this project with my collegue Michele Pugno for the course “Industrial Informatics”. The goal of this project was to develop a component that could receive an op-code and 2 numbers as a serial input, perform arithmetic/logic operations on the numbers, output the result in parallel and also transmit the 2 numbers as a serial output.

All the code was developed in VHDL and tested using ModelSim simulations.

VHDL code, requirements and a small report are available in the Multi-Operation-ALU-VHDL repository.

Testbench 1 Testbench 2 Testbench 3
Waveforms of the final testbenches